1. Field of the Invention
The present invention generally relates to printed circuit cards and boards and processes for mounting devices on the major surfaces thereof.
More particularly, the present invention relates to a method of making reliable connections between lands, aka pads, on at least one of the major surfaces of a carrier, which may be a circuit board, card, flexible substrate or circuitized semiconductor chip or wafer, and a surface mounted device, and the resulting product. The mounted device may include resistors, capacitors, and the like or may itself comprise a board, card, flexible substrate or circuitized semiconductor chip or wafer.
The method and product of the present invention is especially useful in the field known as High Density Circuitry, and the uniqueness of the product especially evident therein. However, it may be used to advantage in any situation in which it is necessary to increase the volume of solder in a discrete area. Because the temperatures and chemicals involved in processing are nondestructive, the method and product are amenable to joining by wave soldering to and between lands on substrates comprising organic materials as well as inorganic and semiconductor materials.
2. Background Art
Printed circuit devices have been used in the electronics industry for many years and in a variety of environments. The flat substrate of insulating material may be thin or thick, and is typically comprised of layers of dielectric material such as epoxy resin, polyimide, polyester and the like, which may be reinforced with fibers and filled with heat conductive, electrically nonconductive particles. Each layer may bear circuitry traces, commonly comprised of copper, which may terminate in small eyelet or square shaped conductive regions called lands. Lands may be provided with through holes and vias in order to interconnect laminated layers within the laminated composite. External lands also provide sites on which to mount components such as resistors, capacitors, integrated circuits and the like.
Over the years, attention has been drawn to printed circuit devices of increasingly smaller and denser physical dimensions combined with increasingly greater functional capacity. The supercomputers being planned now for future manufacture as well as miniaturized electronic devices will depend on the reliable performance of electronic packages of unprecedented complexity as well as unprecedented functionally and dimensionally demanding tolerances. The fabrication of these complex and demanding structures requires the use of many new materials and processes and presents a host of new problems.
Surface mount is a technology which can be used to produce improved packaging efficiency and performance. In surface mount technology (SMT) components with input/output (I/O) leads are typically soldered to lands on the surface of a carrier. A further improvement to the efficient use of carrier real estate is seen when the components are mounted on both major surfaces of the carrier. As discussed in Chapter 19, p. 577 of Principles of Electronic Packaging, Ed. Seraphim et al. 1989, in electronic packaging when a silicon chip is attached to a metallized substrate (chip carrier), the junction is called the first level interconnection. When completed, this assembly is referred to as the component, which is then attached to the next circuitry level, i.e. the printed circuit board, the junction being called the second level interconnection. Current developments focus on directly attaching the chip to the board, eliminating one level of packaging and one level of interconnection. As discussed in Chapter 1, pp. 16 and 42-43 of Microelectronics Packaging Handbook, Ed. Tummala et al. 1989, interconnections have been made by inserting pins and wires into through holes in cards and soldering. SMT, however, provides increased interconnection density, ceramics even smaller. The limit to the number of interconnections possible is determined in large part by the size of the lands and the density of their spacing. The smaller the lands and the more closely spaced, the more devices can be soldered thereto, whether by soldering pins to lands or by Controlled Collapse Chip Connection (C4) technology, also known as flip-chip joining, wherein solder balls make the land to land connection.
The size of the land is directly related to the solder volume that can be applied thereto. The reliability of the soldered interconnection also bears a direct relation to the solder volume. In high density technology, wherein the land size is decreased due to spacing constraints, the volume of solder that can be applied is minimal. It is difficult or impossible under those constraints to apply enough solder reproducibly to a land in order to form a secure joint between a carrier and a mounted device. On the other hand, too much solder causes joint failure due to smearing and shorting. Particularly in the soldering of high density devices no satisfactory way has been known prior to the present invention to obtain the required volume of solder in a controlled, reproducible way, consistently from land to land. Thus the problem is presented of how strong, reliable solder interconnections can be made to lands which are about 4 to about 6 mils in diameter or even smaller. In addition, in case of misalignment or other such initial soldering problem, rework and repair of the solder joint must be accomplished nondestructively in the presence of organic dielectric materials.